An electronic design automation (EDA) tool for inserting dummy tiles between interconnect lines of an integrated circuit design includes a memory for storing the integrated circuit design and a processor in communication with the memory. The processor identifies those interconnect lines that are at different voltage levels, have a length greater than a predefined threshold length and a spacing less than a predefined threshold spacing, and inserts blockage areas between such interconnect lines. The processor skips the blockage areas and adds dummy tiles only between those interconnect lines that do not meet predetermined criteria.