发明授权
US08898671B2 Processor that executes a plurality of threads by promoting efficiency of transfer of data that is shared with the plurality of threads
有权
处理器,其通过提高与所述多个线程共享的数据的传送效率来执行多个线程
- 专利标题: Processor that executes a plurality of threads by promoting efficiency of transfer of data that is shared with the plurality of threads
- 专利标题(中): 处理器,其通过提高与所述多个线程共享的数据的传送效率来执行多个线程
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申请号: US13393967申请日: 2011-07-06
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公开(公告)号: US08898671B2公开(公告)日: 2014-11-25
- 发明人: Hiroyuki Morishita
- 申请人: Hiroyuki Morishita
- 申请人地址: JP Osaka
- 专利权人: Panasonic Corporation
- 当前专利权人: Panasonic Corporation
- 当前专利权人地址: JP Osaka
- 代理机构: Wenderoth, Lind & Ponack, L.L.P.
- 优先权: JP2010-154629 20100707
- 国际申请: PCT/JP2011/003861 WO 20110706
- 国际公布: WO2012/004990 WO 20120112
- 主分类号: G06F9/46
- IPC分类号: G06F9/46 ; G06F9/26 ; G06F13/00 ; G06F12/00 ; G06F7/00 ; G06F9/48 ; G06F9/38 ; G06F9/30
摘要:
Provide is a processor that can maintain a dependency relationship between a plurality of instructions and one read instruction. The processor comprises: a setting unit configured to set, when an instruction that exists at a location ensuring that writing into a memory area has been completed is executed, usage information indicating whether writing into the memory area has been completed such that the usage information indicates that writing into a memory area during execution of one thread has been completed; and a control unit configured to (i) perform execution of a read instruction to read data stored in the memory area when the usage information indicates that writing into the memory area during execution of the one thread has been completed, and (ii) suppress execution of the read instruction when the usage information indicates that writing into the memory area during execution of the one thread has not been completed.
公开/授权文献
- US20120167114A1 PROCESSOR 公开/授权日:2012-06-28
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