Invention Grant
- Patent Title: Method for forming a dual damascene structure of a semiconductor device, and a semiconductor device therewith
- Patent Title (中): 用于形成半导体器件的双镶嵌结构的方法及其半导体器件
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Application No.: US14072881Application Date: 2013-11-06
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Publication No.: US08900997B2Publication Date: 2014-12-02
- Inventor: Joon-Young Moon , Youn-Jin Cho , Sung-Jae Lee , You-Jung Park , Yong-Woon Yoon , Chul-Ho Lee , Chung-Heon Lee
- Applicant: Joon-Young Moon , Youn-Jin Cho , Sung-Jae Lee , You-Jung Park , Yong-Woon Yoon , Chul-Ho Lee , Chung-Heon Lee
- Applicant Address: KR Gumi-si, Kyeongsangbuk-do
- Assignee: Cheil Industries, Inc.
- Current Assignee: Cheil Industries, Inc.
- Current Assignee Address: KR Gumi-si, Kyeongsangbuk-do
- Agency: Lee & Morse, P.C.
- Priority: KR10-2012-0153753 20121226
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L23/522 ; H01L23/532 ; H01L21/768

Abstract:
Forming a dual damascene structure includes forming a first insulation layer and a second insulation layer, forming a resist mask, forming a via hole down to a lower end of the first insulation layer, forming a hardmask layer in the via hole and on the second insulation layer using a spin-coating method, forming a resist mask, forming a first trench hole down to a lower end of the second insulation layer, respectively removing a part of the hardmask layer in the via hole and a part of the hardmask layer on the second insulation layer, forming a second trench hole by removing a part of the first insulation layer between a top corner of the hardmask layer remaining in the via hole and a bottom corner of the first trench hole, removing the hardmask layer, and filling the via hole and the second trench hole with a conductive material.
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Information query
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