发明授权
- 专利标题： Methods of making JFET devices with pin gate stacks
- 专利标题（中）： 制造具有引脚栅极堆叠的JFET器件的方法
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申请号： US14135281申请日： 2013-12-19
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公开(公告)号： US08901625B2公开(公告)日： 2014-12-02
- 发明人: Chandra Mouli
- 申请人： Micron Technology, Inc.
- 申请人地址： US ID Boise
- 专利权人： Micron Technology, Inc.
- 当前专利权人： Micron Technology, Inc.
- 当前专利权人地址： US ID Boise
- 代理机构： Fletcher Yoder PC
- 主分类号： H01L29/66
- IPC分类号： H01L29/66 ; H01L29/808 ; H01L29/10 ; H01L29/80 ; H01L29/15
摘要：
Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a PIN gate stack. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.
公开/授权文献
- US20140110753A1 Methods of Making JFET Devices with Pin Gate Stacks 公开/授权日：2014-04-24
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