发明授权
US08912811B2 Test contact system for testing integrated circuits with packages having an array of signal and power contacts
有权
用于测试具有信号和电源触点阵列的封装的集成电路的测试接触系统
- 专利标题: Test contact system for testing integrated circuits with packages having an array of signal and power contacts
- 专利标题(中): 用于测试具有信号和电源触点阵列的封装的集成电路的测试接触系统
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申请号: US13355913申请日: 2012-01-23
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公开(公告)号: US08912811B2公开(公告)日: 2014-12-16
- 发明人: Jeffrey C. Sherry , Patrick J. Alladio , Russell F. Oberg , Brian K. Warwick
- 申请人: Jeffrey C. Sherry , Patrick J. Alladio , Russell F. Oberg , Brian K. Warwick
- 申请人地址: US MN Minneapolis
- 专利权人: Johnstech International Corporation
- 当前专利权人: Johnstech International Corporation
- 当前专利权人地址: US MN Minneapolis
- 代理机构: Altera Law Group, LLC
- 主分类号: G01R1/067
- IPC分类号: G01R1/067 ; G01R1/073 ; H01L23/00
摘要:
A test fixture (120) is disclosed for electrically testing a device under test (130) by forming a plurality of temporary mechanical and electrical connections between terminals (131) on the device under test (130) and contact pads (161) on the load board (160). The test fixture (120) has a replaceable membrane (150) that includes vias (151), with each via (151) being associated with a terminal (131) on the device under test (130) and a contact pad (161) on the load board (160). In some cases, each via (151) has an electrically conducting wall for conducting current between the terminal (131) and the contact pad (161). In some cases, each via (151) includes a spring (152) that provides a mechanical resisting force to the terminal (131) when the device under test (130) is engaged with the test fixture (120).