In one embodiment, a semiconductor target for detecting overlay error between two or more successive layers of a substrate or between two or more separately generated patterns on a single layer of a substrate is disclosed. The target comprises at least a plurality of a plurality of first grating structures having a course pitch that is resolvable by an inspection tool and a plurality of second grating structures positioned relative to the first grating structures. The second grating structures have a fine pitch that is smaller than the course pitch, and the first and second grating structures are both formed in two or more successive layers of a substrate or between two or more separately generated patterns on a single layer of a substrate. The first and second gratings have feature dimensions that all comply with a predefined design rules specification.