发明授权
US08914611B2 Address translation device, processing device and control method of processing device
有权
地址转换装置,处理装置及处理装置的控制方法
- 专利标题: Address translation device, processing device and control method of processing device
- 专利标题(中): 地址转换装置,处理装置及处理装置的控制方法
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申请号: US13562414申请日: 2012-07-31
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公开(公告)号: US08914611B2公开(公告)日: 2014-12-16
- 发明人: Hiroaki Kimura
- 申请人: Hiroaki Kimura
- 申请人地址: JP Kawasaki
- 专利权人: Fujitsu Limited
- 当前专利权人: Fujitsu Limited
- 当前专利权人地址: JP Kawasaki
- 代理机构: Fujitsu Patent Center
- 优先权: JP2011-209755 20110926
- 主分类号: G06F12/10
- IPC分类号: G06F12/10
摘要:
An address translation buffer (TLB) which holds pairs of virtual addresses and physical addresses by respective page sizes and performs an address translation, a storage unit which holds a pair of a virtual address removed from the TLB and page size corresponding thereto when a pair of a new virtual address and physical address read from a page table is registered to the TLB, base registers which hold a base address by each page size are held. The TLB is searched based on a translation object virtual address included in a memory access request, and when a TLB miss occurs, a main storage is searched based on a pointer address generated from information held by the storage unit and the base register, and the translation object virtual address is translated into the physical address.