A peak current controlled switching voltage regulator system and method for providing a self-power down mode. An on-chip voltage regulator integrated into an on-chip digital logic circuit provides a core supply voltage to the on-chip digital logic circuit along with an off-chip inductor. An off-chip regulator connected to the on-chip digital logic circuit provides an external core supply voltage with respect to the on-chip digital logic circuit. A start-up circuit operates the on-chip voltage regulator in a self-power down mode for a pre-determined time period when the on-chip regulator is not connected to the off-chip inductor in order to maintain an equilibrium voltage supply with respect to the on-chip digital logic circuit.