Disclosed are various embodiments that provide an architecture of memory buffers for a network component configured to process packets. A network component may receive a packet, the packet being associated with a control structure and packet data, an input port set and an output port set. The network component determines one of a plurality of control structure memory partitions for writing the control structure, the one of the plurality of control structure memory partitions being determined based at least upon the input port set and the output port set; and determines one of a plurality of packet data memory partitions for writing the packet data, the one of the plurality of packet data memory partitions being determined independently of the input port set.