Invention Grant
- Patent Title: Diode structure and method for gate all around silicon nanowire technologies
- Patent Title (中): 硅纳米线技术的二极管结构和方法
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Application No.: US13761453Application Date: 2013-02-07
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Publication No.: US08927397B2Publication Date: 2015-01-06
- Inventor: Josephine B. Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Michael J. Chang, LLC
- Agent Louis J. Percello
- Main IPC: H01L21/20
- IPC: H01L21/20 ; H01L21/36 ; H01L29/66 ; H01L27/12 ; B82Y10/00 ; B82Y99/00
Abstract:
A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. At least one first/second set of nanowires and pads are patterned in the SOI layer. A conformal gate dielectric layer is selectively formed surrounding a portion of each of the first set of nanowires that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer surrounding the portion of each of the first set of nanowires that serves as the channel region of the transistor device in a gate all around configuration. A second metal gate stack is formed surrounding a portion of each of the second set of nanowires that serves as a channel region of a diode device in a gate all around configuration.
Public/Granted literature
- US20140217507A1 Diode Structure and Method for Gate All Around Silicon Nanowire Technologies Public/Granted day:2014-08-07
Information query
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