Invention Grant
- Patent Title: Conductive via hole and method for forming conductive via hole
- Patent Title (中): 导电通孔和形成导电通孔的方法
-
Application No.: US12969469Application Date: 2010-12-15
-
Publication No.: US08927433B2Publication Date: 2015-01-06
- Inventor: Jin-Yeong Kang
- Applicant: Jin-Yeong Kang
- Applicant Address: KR Daejeon
- Assignee: Electronics and Telecommunications Research Institute
- Current Assignee: Electronics and Telecommunications Research Institute
- Current Assignee Address: KR Daejeon
- Priority: KR10-2009-0126704 20091218; KR10-2010-0035906 20100419
- Main IPC: H01L21/311
- IPC: H01L21/311 ; H01L21/768 ; H01L21/288 ; H01L23/48
Abstract:
Provided is a technology for forming a conductive via hole to implement a three dimensional stacked structure of an integrated circuit. A method for forming a conductive via hole according to an embodiment of the present invention comprises: filling inside of a via hole structure that is formed in one or more of an upper portion and a lower portion of a substrate with silver by using a reduction and precipitation of silver in order to connect a plurality of stacked substrates by a conductor; filling a portion that is not filled with silver inside of the via hole structure by flowing silver thereinto; and sublimating residual material of silver oxide series, which is generated during the flowing, on an upper layer inside of the via hole structure filled with silver.
Public/Granted literature
- US20110147938A1 CONDUCTIVE VIA HOLE AND METHOD FOR FORMING CONDUCTIVE VIA HOLE Public/Granted day:2011-06-23
Information query
IPC分类:
