发明授权
US08929422B2 Clock distribution architecture for dual integrated core engine transceiver for use in radio system
有权
用于无线电系统的双集成核心引擎收发器的时钟分配架构
- 专利标题: Clock distribution architecture for dual integrated core engine transceiver for use in radio system
- 专利标题(中): 用于无线电系统的双集成核心引擎收发器的时钟分配架构
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申请号: US13465269申请日: 2012-05-07
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公开(公告)号: US08929422B2公开(公告)日: 2015-01-06
- 发明人: Boris Radovcic , Michael S. Vogas
- 申请人: Boris Radovcic , Michael S. Vogas
- 申请人地址: US NH Nashua
- 专利权人: BAE Systems Information and Electronic Systems Integration Inc.
- 当前专利权人: BAE Systems Information and Electronic Systems Integration Inc.
- 当前专利权人地址: US NH Nashua
- 代理商 Daniel J. Long
- 主分类号: H04B13/02
- IPC分类号: H04B13/02 ; H04L7/00
摘要:
A method and apparatus of minimizing corruption of a reference clock to a RF circuitry in a radio system is disclosed. A DICE-T receives a reference clock in a Low Voltage Differential Signal (LVDS) format from a GVA. The DICE-T personality card converts the reference clock signal into an analog signal. The analog signal is supplied to the Core Engine RF card and the LVDS format signal is supplied to the Core Engine modem for local clocking. The Core Engine RF feeds the analog signal into a programmable phase locked loop chip to generate all the clocks required for RF processing. The analog signal is also used to provide the clocks to the ADC and DAC of core engine modem. By routing the reference clock directly to the RF card then deriving the modem clocks, the phase noise of the reference clock is reduced.
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