发明授权
- 专利标题: Method for locking a delay locked loop
- 专利标题(中): 锁定延迟锁定环路的方法
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申请号: US14147458申请日: 2014-01-03
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公开(公告)号: US08937499B2公开(公告)日: 2015-01-20
- 发明人: Shawn Searles
- 申请人: Advanced Micro Devices, Inc.
- 申请人地址: US CA Sunnyvale
- 专利权人: Advanced Micro Devices, Inc.
- 当前专利权人: Advanced Micro Devices, Inc.
- 当前专利权人地址: US CA Sunnyvale
- 代理机构: Volpe and Koenig, P.C.
- 主分类号: H03L7/06
- IPC分类号: H03L7/06 ; H03L7/10 ; H03L7/081
摘要:
A method and apparatus for synchronizing a delay line to a reference clock. A delay line receives a clock input signal based on a reference clock and outputs a delay edge signal according to a control signal. An injector receives a first edge of the reference clock and in response to a first trigger, sends the clock input signal to the delay line. A synchronizer determines that the first edge has passed through the delay line, and in response, sends the injector a second trigger to send a second edge of the clock input signal to the delay line. An edge detector compares the timing of the first edge of the delay edge signal to a timing of the first edge of the reference edge signal. A control signal is sent to the delay line to decrease or increase the delay setting of the delay line based on the comparison.
公开/授权文献
- US20140118042A1 METHOD FOR LOCKING A DELAY LOCKED LOOP 公开/授权日:2014-05-01
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