Invention Grant
US08946029B2 Methods of manufacturing integrated circuits having FinFET structures with epitaxially formed source/drain regions
有权
制造具有外延形成的源/漏区的FinFET结构的集成电路的方法
- Patent Title: Methods of manufacturing integrated circuits having FinFET structures with epitaxially formed source/drain regions
- Patent Title (中): 制造具有外延形成的源/漏区的FinFET结构的集成电路的方法
-
Application No.: US13674142Application Date: 2012-11-12
-
Publication No.: US08946029B2Publication Date: 2015-02-03
- Inventor: Hoong Shing Wong , Min-hwa Chi
- Applicant: GLOBALFOUNDRIES, Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES, Inc.
- Current Assignee: GLOBALFOUNDRIES, Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Ingrassia Fisher & Lorenz, P.C.
- Main IPC: H01L29/78
- IPC: H01L29/78

Abstract:
Methods of manufacturing semiconductor integrated circuits having FinFET structures with epitaxially formed source and drain regions are disclosed. For example, a method of fabricating an integrated circuit includes forming a plurality of silicon fin structures on a semiconductor substrate, forming disposable spacers on vertical sidewalls of the fin structures, and depositing a silicon oxide material over the fins and over the disposable spacers. The method further includes anisotropically etching at least one of the fin structures and the disposable spacers on the sidewalls of the at least one fin structure, thereby leaving a void in the silicon oxide material, and etching the silicon oxide material and the disposable spacers from at least one other of the fin structures, while leaving the at least one other fin structure un-etched. Still further, the method includes epitaxially growing a silicon material in the void and on the un-etched fin structure. An un-merged source/drain region is formed in the void and a merged source/drain region is formed on the un-etched fin structure.
Public/Granted literature
Information query
IPC分类: