Disclosed herein are an apparatus and method for controlling memory. The apparatus includes a memory access request buffer unit, a memory access request control unit, and a bank control unit. The memory access request buffer unit determines and stores memory access request order so that the plurality of memory access requests is processed in the order of input except that memory access requests attempting to access the same bank and the same row are successively processed. The memory access request control unit reads the memory access requests from the memory access request buffer unit in the determined order, distributes the memory access requests to banks, and transfers the memory access requests to memory. The bank control unit stores a preset number of memory access requests in each of buffer units for respective banks, and controls the operating state of each of the banks.