Invention Grant
US08956789B2 Methods for fabricating integrated circuits including multi-patterning of masks for extreme ultraviolet lithography
有权
用于制造集成电路的方法,包括用于极紫外光刻的掩模的多图案化
- Patent Title: Methods for fabricating integrated circuits including multi-patterning of masks for extreme ultraviolet lithography
- Patent Title (中): 用于制造集成电路的方法,包括用于极紫外光刻的掩模的多图案化
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Application No.: US13832994Application Date: 2013-03-15
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Publication No.: US08956789B2Publication Date: 2015-02-17
- Inventor: Sudharshanan Raghunathan
- Applicant: GLOBALFOUNDRIES, Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES, Inc.
- Current Assignee: GLOBALFOUNDRIES, Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Ingrassia Fisher & Lorenz, P.C.
- Main IPC: H01L21/66
- IPC: H01L21/66

Abstract:
Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes patterning a first photoresist layer overlying a mask blank that is mounted on a first chuck to form a first patterned photoresist layer. The mask blank is selectively etched using the first patterned photoresist layer to form a first patterned mask. The first patterned mask is mounted on a second chuck and a non-flatness compensation is determined. The first patterned mask is mounted on the first chuck and a second photoresist layer is patterned overlying the first patterned mask to form a second patterned photoresist layer. The second patterned photoresist layer includes a device pattern that has been adjusted using the non-flatness compensation. The first patterned mask is selectively etched using the second patterned photoresist layer to form a second patterned mask.
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