发明授权
US08956889B2 Method of testing through silicon VIAS (TSVs) of three dimensional integrated circuit (3DIC)
有权
通过三维集成电路（3DIC）的硅VIAS（TSV）测试方法
- 专利标题： Method of testing through silicon VIAS (TSVs) of three dimensional integrated circuit (3DIC)
- 专利标题（中）： 通过三维集成电路（3DIC）的硅VIAS（TSV）测试方法
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申请号： US13800626申请日： 2013-03-13
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公开(公告)号： US08956889B2公开(公告)日： 2015-02-17
- 发明人: Hung-Chih Lin , Mill-Jer Wang , Ching-Nen Peng , Hao Chen
- 申请人： Hung-Chih Lin , Mill-Jer Wang , Ching-Nen Peng , Hao Chen
- 申请人地址： TW
- 专利权人： Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人： Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人地址： TW
- 代理机构： Lowe Hauptman & Ham, LLP
- 主分类号： H01L21/66
- IPC分类号： H01L21/66 ; H01L23/00 ; H01L25/065 ; H01L25/00
摘要：
In a method of testing a plurality of through silicon vias (TSVs) chained together by interconnect on a substrate, a test signal is applied to a first test pad among a plurality of test pads, and a return signal is measured at a second test pad among the plurality of test pads. At least one test pad of the plurality of test pads is grounded to the substrate. The remaining test pads of the plurality of test pads are either connected to the plurality of chained TSVs or are grounded.
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