Invention Grant
US08956889B2 Method of testing through silicon VIAS (TSVs) of three dimensional integrated circuit (3DIC)
有权
通过三维集成电路（3DIC）的硅VIAS（TSV）测试方法
- Patent Title: Method of testing through silicon VIAS (TSVs) of three dimensional integrated circuit (3DIC)
- Patent Title (中): 通过三维集成电路（3DIC）的硅VIAS（TSV）测试方法
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Application No.: US13800626Application Date: 2013-03-13
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Publication No.: US08956889B2Publication Date: 2015-02-17
- Inventor: Hung-Chih Lin , Mill-Jer Wang , Ching-Nen Peng , Hao Chen
- Applicant: Hung-Chih Lin , Mill-Jer Wang , Ching-Nen Peng , Hao Chen
- Applicant Address: TW
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW
- Agency: Lowe Hauptman & Ham, LLP
- Main IPC: H01L21/66
- IPC: H01L21/66 ; H01L23/00 ; H01L25/065 ; H01L25/00
Abstract:
In a method of testing a plurality of through silicon vias (TSVs) chained together by interconnect on a substrate, a test signal is applied to a first test pad among a plurality of test pads, and a return signal is measured at a second test pad among the plurality of test pads. At least one test pad of the plurality of test pads is grounded to the substrate. The remaining test pads of the plurality of test pads are either connected to the plurality of chained TSVs or are grounded.
Public/Granted literature
- US20130196458A1 METHOD OF TESTING THROUGH SILICON VIAS (TSVS) OF THREE DIMENSIONAL INTEGRATED CIRCUIT (3DIC) Public/Granted day:2013-08-01
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