Invention Grant
- Patent Title: Limit equalizer output based timing loop
- Patent Title (中): 限制基于均衡器输出的定时循环
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Application No.: US13608365Application Date: 2012-09-10
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Publication No.: US08957793B1Publication Date: 2015-02-17
- Inventor: Jingfeng Liu , Mats Oberg , Zachary Keirn , Bin Ni
- Applicant: Jingfeng Liu , Mats Oberg , Zachary Keirn , Bin Ni
- Applicant Address: BM Hamilton
- Assignee: Marvell International Ltd.
- Current Assignee: Marvell International Ltd.
- Current Assignee Address: BM Hamilton
- Main IPC: H03M1/48
- IPC: H03M1/48

Abstract:
Aspects of the disclosure provide a method. The method includes boosting a portion of frequency components of a digital signal that is converted from an analog signal based on a clock signal, generating a decision signal based on the boosted digital signal, generating a timing error signal based on the boosted digital signal and the decision signal, and filtering the timing error signal to generate a voltage signal to control a voltage controlled oscillator to generate the clock signal.
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