Invention Grant
US08966232B2 Data processing system operable in single and multi-thread modes and having multiple caches and method of operation
有权
数据处理系统可在单线程和多线程模式下运行，并具有多个高速缓存和操作方法
- Patent Title: Data processing system operable in single and multi-thread modes and having multiple caches and method of operation
- Patent Title (中): 数据处理系统可在单线程和多线程模式下运行，并具有多个高速缓存和操作方法
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Application No.: US13370420Application Date: 2012-02-10
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Publication No.: US08966232B2Publication Date: 2015-02-24
- Inventor: Thang M. Tran
- Applicant: Thang M. Tran
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F9/38
Abstract:
In some embodiments, a data processing system includes a processing unit, a first load/store unit LSU and a second LSU configured to operate independently of the first LSU in single and multi-thread modes. A first store buffer is coupled to the first and second LSUs, and a second store buffer is coupled to the first and second LSUs. The first store buffer is used to execute a first thread in multi-thread mode. The second store buffer is used to execute a second thread in multi-thread mode. The first and second store buffers are used when executing a single thread in single thread mode.
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