Invention Grant
- Patent Title: Bump structures for semiconductor package
- Patent Title (中): 半导体封装的凸块结构
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Application No.: US13624356Application Date: 2012-09-21
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Publication No.: US08970035B2Publication Date: 2015-03-03
- Inventor: Jing-Cheng Lin , Po-Hao Tsai
- Applicant: Jing-Cheng Lin , Po-Hao Tsai
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52
Abstract:
A package structure includes a first substrate bonded to a second substrate by Connecting metal pillars on the first substrate to connectors on the second substrate. A first metal pillar is formed overlying and electrically connected to a metal pad on a first region of the first substrate, and a second metal pillar is formed overlying a passivation layer in a second region of the first substrate. A first solder joint region is formed between metal pillar and the first connector, and a second solder joint region is formed between the second metal pillar and the second connector. The thickness of the first metal pillar is greater than the thickness of the second metal pillar.
Public/Granted literature
- US20140061897A1 Bump Structures for Semiconductor Package Public/Granted day:2014-03-06
Information query
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