Invention Grant
- Patent Title: Techniques for utilizing translation lookaside buffer entry numbers to improve processor performance
- Patent Title (中): 使用翻译后备缓冲区入口号来提高处理器性能的技术
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Application No.: US13630346Application Date: 2012-09-28
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Publication No.: US08984254B2Publication Date: 2015-03-17
- Inventor: Thang M. Tran , Edmund J. Gieske
- Applicant: Thang M. Tran , Edmund J. Gieske
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agency: Yudell Isidore PLLC
- Main IPC: G06F12/10
- IPC: G06F12/10
Abstract:
A technique for operating a processor includes translating, using an associated translation lookaside buffer, a first virtual address into a first physical address through a first entry number in the translation lookaside buffer. The technique also includes translating, using the translation lookaside buffer, a second virtual address into a second physical address through a second entry number in the translation lookaside buffer. The technique further includes, in response to the first entry number being the same as the second entry number, determining that the first and second virtual addresses point to the same physical address in memory and reference the same data.
Public/Granted literature
- US20140095784A1 Techniques for Utilizing Transaction Lookaside Buffer Entry Numbers to Improve Processor Performance Public/Granted day:2014-04-03
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