Invention Grant
- Patent Title: Techniques for storing ECC checkbits in a level two cache
- Patent Title (中): 将ECC校验位存储在二级缓存中的技术
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Application No.: US13683599Application Date: 2012-11-21
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Publication No.: US08984372B2Publication Date: 2015-03-17
- Inventor: Wishwesh Anil Gandhi , Nirmal Raj Saxena
- Applicant: NVIDIA Corporation
- Applicant Address: US CA Santa Clara
- Assignee: NVIDIA Corporation
- Current Assignee: NVIDIA Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Artegis Law Group, LLP
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G06F11/10

Abstract:
A partition unit that includes a cache for storing both data and error-correcting code (ECC) checkbits associated with the data is disclosed. When a read command corresponding to particular data stored in a memory unit results in a cache miss, the partition unit transmits a read request to the memory unit to fetch the data and store the data in the cache. The partition unit checks the cache to determine if ECC checkbits associated with the data are stored in the cache and, if the ECC checkbits are not in the cache, the partition unit transmits a read request to the memory unit to fetch the ECC checkbits and store the ECC checkbits in the cache. The ECC checkbits and the data may then be compared to determine the reliability of the data using an error-correcting scheme such as SEC-DED (i.e., single error-correcting, double error-detecting).
Public/Granted literature
- US20140143635A1 TECHNIQUES FOR STORING ECC CHECKBITS IN A LEVEL TWO CACHE Public/Granted day:2014-05-22
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