Invention Grant
- Patent Title: Drain induced barrier lowering with anti-punch-through implant
- Patent Title (中): 通过抗穿通植入物引起的排水诱导的屏障降低
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Application No.: US13719511Application Date: 2012-12-19
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Publication No.: US08987748B2Publication Date: 2015-03-24
- Inventor: Himadri Sekhar Pal , Youn Sung Choi , Amitabh Jain
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Jacqueline J. Garner; Frederick J. Telecky, Jr.
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/66 ; H01L21/8238

Abstract:
An integrated circuit containing an MOS transistor with epitaxial source and drain regions may be formed by implanting a retrograde anti-punch-through layer prior to etching the source drain regions for epitaxial replacement. The anti-punch-through layer is disposed between stressor tips of the epitaxial source and drain regions, and does not substantially extend into the epitaxial source and drain regions.
Public/Granted literature
- US20130161639A1 DRAIN INDUCED BARRIER LOWERING WITH ANTI-PUNCH-THROUGH IMPLANT Public/Granted day:2013-06-27
Information query
IPC分类: