Invention Grant
- Patent Title: Prevention of faceting in epitaxial source drain transistors
- Patent Title (中): 防止外延源极漏极晶体管中的刻面
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Application No.: US13907690Application Date: 2013-05-31
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Publication No.: US08987827B2Publication Date: 2015-03-24
- Inventor: Pietro Montanini , Raymond Joy , Marta Mottura , Henry K. Utomo
- Applicant: STMicroelectronics, Inc. , International Business Machines Corporation , GLOBALFOUNDRIES Inc.
- Applicant Address: US TX Coppell US NY Armonk KY Grand Cayman
- Assignee: STMicroelectronics, Inc.,International Business Machines Corporation,GLOBALFOUNDRIES, Inc.
- Current Assignee: STMicroelectronics, Inc.,International Business Machines Corporation,GLOBALFOUNDRIES, Inc.
- Current Assignee Address: US TX Coppell US NY Armonk KY Grand Cayman
- Agency: Seed IP Law Group PLLC
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/78
Abstract:
A method for fabricating enhanced-mobility pFET devices having channel lengths below 50 nm. Gates for pFETs may be patterned in dense arrays on a semiconductor substrate that includes shallow trench isolation (STI) structures. Partially-enclosed voids in the semiconductor substrate may be formed at source and drain regions for the gates, and subsequently filled with epitaxially-grown semiconductor that compressively stresses channel regions below the gates. Some of the gates (dummy gates) may extend over edges of the STI structures to prevent undesirable faceting of the epitaxial material in the source and drain regions.
Public/Granted literature
- US20140353741A1 BOTTLED EPITAXY IN SOURCE AND DRAIN REGIONS OF FETS Public/Granted day:2014-12-04
Information query
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