Invention Grant
- Patent Title: Systems and methods for lowering interconnect capacitance
- Patent Title (中): 降低互连电容的系统和方法
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Application No.: US13674535Application Date: 2012-11-12
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Publication No.: US08994150B2Publication Date: 2015-03-31
- Inventor: Timothy Hollis
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: H01L29/72
- IPC: H01L29/72 ; H01L23/48 ; H01L23/50 ; H01L25/18 ; H01L23/00
Abstract:
Methods and apparatus for lowering the capacitance of an interconnect, are disclosed. An example apparatus may include an interconnect formed in at least one integrated circuit and configured to pass a signal through at least a portion of the at least one integrated circuit. The apparatus may include a transmitter to operate at a first voltage and a second voltage, and to output to an end node of the interconnect a reduced swing signal ranging from the first voltage to a third voltage. The third voltage may be between the first and second voltages, and the reduced swing signal may operate to reduce a capacitance of the interconnect when compared to operating the transmitter at the second voltage. Additional apparatus and methods are disclosed.
Public/Granted literature
- US20130069705A1 SYSTEMS AND METHODS FOR LOWERING INTERCONNECT CAPACITANCE Public/Granted day:2013-03-21
Information query
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