发明授权
US09002765B1 Stable parallel loop systems 有权
稳定并联回路系统

  • 专利标题: Stable parallel loop systems
  • 专利标题(中): 稳定并联回路系统
  • 申请号: US13295013
    申请日: 2011-11-11
  • 公开(公告)号: US09002765B1
    公开(公告)日: 2015-04-07
  • 发明人: Muralidhar Ravuri
  • 申请人: Muralidhar Ravuri
  • 代理机构: Spano Law Group
  • 代理商 Joseph S. Spano
  • 主分类号: G06N3/04
  • IPC分类号: G06N3/04 G06N3/08
Stable parallel loop systems
摘要:
Stable Parallel Loop (SPL) systems and exemplary embodiments are described with reference to both software and hardware platforms. A SPL network includes an input surface, internal nodes, connections that selectively link internal nodes, and an output surface. Signals from the environment are received on the input surface. The received signals excite internal nodes of the SPL network. The internal nodes exhibit their own dynamic behavior. As a result of the interconnected network structure and operational characteristics of each node, dynamic loops are formed among certain internal nodes. A dynamic loop is formed when all of internal nodes within an interconnected loop are active. Output from the SPL network is generated based on the dynamic loops that are formed. Tools to develop and implement a SPL network are presented.
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