Invention Grant
- Patent Title: Negative edge reset flip-flop with dual-port slave latch
- Patent Title (中): 带双端口从机锁存器的负沿复位触发器
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Application No.: US14154458Application Date: 2014-01-14
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Publication No.: US09007111B2Publication Date: 2015-04-14
- Inventor: Steven Bartling , Sudhanshu Khanna
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent John R. Pessetto; Frank D. Cimino
- Main IPC: H03K3/356
- IPC: H03K3/356 ; H03K3/3562

Abstract:
In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CKT and CLKN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, SS, SS, RE and REN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.
Public/Granted literature
- US20140232442A1 NEGATIVE EDGE RESET FLIP-FLOP WITH DUAL-PORT SLAVE LATCH Public/Granted day:2014-08-21
Information query
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