Invention Grant
- Patent Title: Memory circuit and memory device
- Patent Title (中): 存储器电路和存储器件
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Application No.: US13683257Application Date: 2012-11-21
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Publication No.: US09007816B2Publication Date: 2015-04-14
- Inventor: Takuro Ohmaru
- Applicant: Semiconductor Energy Laboratory Co., Ltd.
- Applicant Address: JP Kanagawa-ken
- Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee Address: JP Kanagawa-ken
- Agency: Fish & Richardson P.C.
- Priority: JP2011-256890 20111125
- Main IPC: G11C11/00
- IPC: G11C11/00 ; G11C7/12 ; G11C11/412 ; G11C11/419

Abstract:
To reduce power consumption, a memory circuit includes a latch unit in which first data and second data are rewritten and read in accordance with a control signal, a first switch unit that controls rewrite and read of the first data stored in the latch unit by being turned on or off in response to the control signal, and a second switch unit that controls rewrite and read of the second data stored in the latch unit by being turned on or off in response to the control signal. The latch unit includes a first inverter and a second inverter. At least one of the first inverter and the second inverter includes a first field-effect transistor, and a second field-effect transistor that has the same conductivity type as the first field-effect transistor and has a gate potential controlled in accordance with the control signal.
Public/Granted literature
- US20130135943A1 MEMORY CIRCUIT AND MEMORY DEVICE Public/Granted day:2013-05-30
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