A semiconductor memory device includes a first data bus having a first width, and a second data bus which is separate from the first data bus and which has a second width which is different from the first width. The semiconductor memory device further includes a data transfer unit configured for transferring data from memory cells connected to a plurality of bit lines. In a first operational mode, the data transfer unit connects a first number of bit lines from among the plurality of bit lines to the first data bus to transfer the data, the first number being equal to the first width. In a second operational mode, the data transfer unit connects a second number of bit lines from among the plurality of bit lines to the second data bus to transfer the data, the second number being equal to the second width.