A memory includes first to Nth word lines, first to Mth redundancy word lines configured to replace M number of word lines among the first to Nth word lines, and a control circuit configured to activate at least one adjacent word line adjacent to a Kth redundancy word line (1≦K≦M) in response to an active signal, in the case where a word line corresponding to an inputted address among the first to Nth word lines is replaced with the Kth redundancy word line among the first to Mth redundancy word lines in a first mode.