Invention Grant
- Patent Title: Area-efficient distributed device structure for integrated voltage regulators
- Patent Title (中): 集成稳压器的区域效率分布式器件结构
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Application No.: US13841099Application Date: 2013-03-15
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Publication No.: US09018046B2Publication Date: 2015-04-28
- Inventor: Joshipura Jwalant , Nitin Bansal , Amit Katyal , Massimiliano Picca
- Applicant: STMicroelectronics International N.V. , STMicroelectronics S.r.l
- Applicant Address: NL Amsterdam IT Agrate Brianza (MB)
- Assignee: STMicroelectronics International N.V.,STMicroelectronics S.r.l.
- Current Assignee: STMicroelectronics International N.V.,STMicroelectronics S.r.l.
- Current Assignee Address: NL Amsterdam IT Agrate Brianza (MB)
- Agency: Gardere Wynne Sewell LLP
- Priority: IN2613/DEL/2004 20041231
- Main IPC: H01L21/82
- IPC: H01L21/82 ; H05K3/30 ; G06F17/50
Abstract:
An area efficient distributed device for integrated voltage regulators comprising at least one filler cell coupled between a pair of PADS on I/O rail of a chip and at least one additional filler cell having small size portion of said device is coupled to said I/O rails for distributing portions of said device on the periphery of said chip. The device is coupled as small size portion on the lower portion of said second filler cell for distributing said device on the periphery of said chip and providing maximal area utilization.
Public/Granted literature
- US20130205587A1 AREA-EFFICIENT DISTRIBUTED DEVICE STRUCTURE FOR INTEGRATED VOLTAGE REGULATORS Public/Granted day:2013-08-15
Information query
IPC分类:
