Invention Grant
- Patent Title: Method for forming a Ge on III/V-on-insulator structure
- Patent Title (中): 用于在III / V绝缘体上形成Ge的方法
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Application No.: US13399273Application Date: 2012-02-17
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Publication No.: US09018678B2Publication Date: 2015-04-28
- Inventor: Nicolas Daval , Bich-Yen Nguyen , Cecile Aulnette , Konstantin Bourdelle
- Applicant: Nicolas Daval , Bich-Yen Nguyen , Cecile Aulnette , Konstantin Bourdelle
- Applicant Address: FR Bernin
- Assignee: Soitec
- Current Assignee: Soitec
- Current Assignee Address: FR Bernin
- Agency: TraskBritt
- Priority: FR1151939 20110309
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/786 ; H01L21/762 ; H01L29/66
Abstract:
The present invention concerns a method for forming a Semiconductor-On-Insulator structure that includes a semiconductor layer of III/V material by growing a relaxed germanium layer on a donor substrate; growing at least one layer of III/V material on the layer of germanium; forming a cleaving plane in the relaxed germanium layer; transferring a cleaved part of the donor substrate to a support substrate, with the cleaved part being a part of the donor substrate cleaved at the cleaving plane that includes the at least one layer of III/V material. The present invention also concerns a germanium on III/V-On-Insulator structure, an N Field-Effect Transistor (NFET), a method for manufacturing an NFET, a P Field-Effect Transistor (PFET), and a method for manufacturing a PFET.
Public/Granted literature
- US20120228672A1 METHOD FOR FORMING A GE ON III/V-ON-INSULATOR STRUCTURE Public/Granted day:2012-09-13
Information query
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