Invention Grant
- Patent Title: Integrated circuit floorplan for compact clock distribution
- Patent Title (中): 集成电路平面图,实现紧凑的时钟分配
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Application No.: US13787647Application Date: 2013-03-06
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Publication No.: US09032358B2Publication Date: 2015-05-12
- Inventor: Vaishnav Srinivas , Robert Won Chol Kim , Philip Michael Clovis , David Ian West
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Arent Fox LLP
- Main IPC: G06F17/50
- IPC: G06F17/50 ; H01L27/02

Abstract:
An integrated circuit includes core logic and a plurality of interface blocks disposed about a periphery of the core logic. A plurality of input or output (I/O) circuits is assigned to one of the plurality of interface blocks. The I/O circuits include external I/O circuits coupled to a device other than the integrated circuit and internal I/O circuits coupled to the integrated circuit. Each interface block includes a first plurality of I/O circuits disposed on a first side of the interface block and a second plurality of I/O circuits disposed on a second side of the interface block. Each interface block also includes interface logic for the interface block between the first plurality of I/O circuits and the second plurality of I/O circuits, and a logic hub that includes a clock distribution of minimal length that drives launch logic and capture logic to form the I/O circuits of the interface block.
Public/Granted literature
- US20140253228A1 INTEGRATED CIRCUIT FLOORPLAN FOR COMPACT CLOCK DISTRIBUTION Public/Granted day:2014-09-11
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