A circuit includes: a first adder configured to add a first offset cancellation value to an input signal value; a second adder configured to add a first equalization value to an output signal value from the first adder; a first comparator configured to make a binary decision on an output signal value from the second adder; a third adder configured to add a second offset cancellation value to the input signal value; a fourth adder configured to add a second equalization value to an output signal value from the third adder; a second comparator configured to make a binary decision on an output signal value from the fourth adder; a selector configured to output a determination result of the first comparator or a determination result of the second comparator in accordance with a determination result of preceding one bit of the input signal value.