Invention Grant
- Patent Title: Method and apparatus for word line suppression
- Patent Title (中): 用于字线抑制的方法和装置
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Application No.: US13279375Application Date: 2011-10-24
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Publication No.: US09064550B2Publication Date: 2015-06-23
- Inventor: Jonathan Tsung-Yung Chang , Chiting Cheng , Chien-Kuo Su , Chung-Cheng Chou , Jack Liu
- Applicant: Jonathan Tsung-Yung Chang , Chiting Cheng , Chien-Kuo Su , Chung-Cheng Chou , Jack Liu
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Duane Morris LLP
- Main IPC: G11C11/00
- IPC: G11C11/00 ; G11C8/08 ; G11C11/418

Abstract:
A memory access operation on a bit cell of a digital memory, e.g., a static random access memory (SRAM), is assisted by reducing the word line control voltage for reading and boosting it for writing, thus improving data integrity. The bit cell has cross coupled inverters for storing and retrieving a logic state via bit line connections through a passing gate transistor controlled by the word line. A level of a word line signal controlling the passing gate transistor is shifted from a first voltage value to a higher second voltage value to begin a memory access cycle. The level of the word line signal is shifted from the second voltage value to a third voltage value less than the second voltage value during the access cycle. The word line signal is maintained at the third voltage value for a time interval during the access cycle.
Public/Granted literature
- US20130100730A1 METHOD AND APPARATUS FOR WORD LINE SUPPRESSION Public/Granted day:2013-04-25
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