A DC-DC converter generates PWM signals PWM1H, PWM1L on the basis of a reference signal CLK1 to drive switching elements connected in series. When generating a reset signal RST, the converter generates PWM signals PWM2H, PWM2L on the basis of the reset signal RST. When generating no reset signal, the converter generates the PWM signals PWM2H, PWM2L on the basis of a reference signal CLK2 in order to drive other switching elements connected in series. The converter generates the reset signal RST at an optional timing to the reference signal CLK1. The reference signal CLK2 is brought forward from the reference signal CLK1 by ΔT1. The PWM signals PWM1H, PWM1L are different in timing from the PWM signals PWM2H, PWM2L. This makes it possible to avoid the switching elements diagonally arranged from being simultaneously turned on and off, and suppress a switching loss, and to increase an efficiency of the converter.