Presented is a random non-cyclical binary code generator for communications systems. A random non-cyclical sequence of integers from a random number generator is extended in length to form an extended integer sequence. This integer set is immediately loaded into a 10-minute epoch memory consistent with 10 minutes of chips. These integers are then synchronously retrieved from memory under GPS time-of-day control. Retrieved integers are immediately converted into pulse pairs of all ones followed by all zeros with each pulse width equal to the integer value in chips. The chips are immediately concatenated to a chipping clock shifting memory wherein each memory location is a unique phase source of the binary code. The memory length in chips is twice the range uncertainty for a 10 MHz chip rate, with the center chip of the shifting memory maintained as the source of universal time synchronized local binary code.