An information processing apparatus which includes at least two controllers and is capable of positively detecting a startup error. Memory devices are connected to the controllers, respectively. A CPU of each controller accesses the memory device connected to the other controller via a bus bridge, identifies a startup stage to which the startup process has proceeded during the start of the self-controller, writes the identified startup stage as startup information into the memory device connected to the other controller, and detects whether or not an abnormality occurs during the startup of the other controller with reference to the startup information written into the memory device connected to the self-controller.