Invention Grant
- Patent Title: Methods for fabricating integrated circuits using surface modification to selectively inhibit etching
- Patent Title (中): 使用表面改性制造集成电路以选择性地抑制蚀刻的方法
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Application No.: US14071070Application Date: 2013-11-04
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Publication No.: US09076846B2Publication Date: 2015-07-07
- Inventor: Errol Todd Ryan , Kunaljeet Tanwar , Xunyuan Zhang
- Applicant: GLOBALFOUNDRIES, Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES, INC.
- Current Assignee: GLOBALFOUNDRIES, INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Ingrassia Fisher & Lorenz, P.C.
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L21/768

Abstract:
Methods for fabricating integrated circuits are provided in various exemplary embodiments. In one embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having a first exposed surface including an elemental metal material and a second exposed surface including a barrier material. The elemental metal material has a first etch rate when exposed to a wet etchant and the barrier material has a second etch rate when exposed to the wet etchant. Further, the method includes modifying the first exposed surface to form a modified first exposed surface so as to reduce the first etch rate when exposed to the wet etchant and applying the wet etchant simultaneously to the modified first exposed surface and to the second exposed surface.
Public/Granted literature
- US20150126028A1 METHODS FOR FABRICATING INTEGRATED CIRCUITS USING SURFACE MODIFICATION TO SELECTIVELY INHIBIT ETCHING Public/Granted day:2015-05-07
Information query
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