An image sensor includes multiple counters and a counter controller. Each counter of the multiple counters is configured to perform counting of a comparison result signal and to generate a count result, the comparison result signal being obtained by comparing a ramp signal and a pixel signal of a column of multiple columns. The counter controller is configured to generate and transmit a counter clock signal and (n−1) delay clock signals to the counters, respectively, “n” being a natural number equal to or greater than two. Each delay clock signal of the (n−1) delay clock signals is obtained by delaying the counter clock signal by a corresponding offset code.