Method for etching target layer of semiconductor device in etching apparatus

Invention Grant

US09087793B2 Method for etching target layer of semiconductor device in etching apparatus 有权

Title translation: 蚀刻装置中的半导体装置的目标层的蚀刻方法

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Patent Title: Method for etching target layer of semiconductor device in etching apparatus
Patent Title (中): 蚀刻装置中的半导体装置的目标层的蚀刻方法
Application No.: US14103681

Application Date: 2013-12-11
Publication No.: US09087793B2

Publication Date: 2015-07-21
Inventor: Han-Wen Liao , Wei-Tai Lin , Wen-Sheng Wang , Chih-Yu Lin , Cherng-Chang Tsuei , Chen-Hsiang Lu
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Applicant Address: TW Hsinchu
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Current Assignee Address: TW Hsinchu
Agency: McDermott Will & Emery LLP
Main IPC: H01L21/308
IPC: H01L21/308

Method for etching target layer of semiconductor device in etching apparatus

Abstract:

A method for etching a target layer of a semiconductor device in an etching apparatus is provided. To form an element, the method includes forming a photoresist pattern on the target layer of the semiconductor device, in which the photoresist pattern has an after-develop-inspection critical dimension (ADI CD). A target after-etch-inspection critical dimension (AEI CD) of the element is provided, as well as a trim time of the target layer. The etching apparatus is provided and a formation time of a protective layer on an inner wall of the etching apparatus is determined based on the ADI CD, the target AEI CD and the trim time. The protective layer for the predetermined formation time is formed to perform a trimming process on the target layer for the trim time by using the photoresist pattern as a mask, so as to form the element.

Abstract(Chinese):

提供了一种在蚀刻装置中蚀刻半导体器件的目标层的方法。为了形成元件，该方法包括在半导体器件的目标层上形成光致抗蚀剂图案，其中光致抗蚀剂图案具有显影后检查临界尺寸（ADI CD）。提供元件的目标蚀刻后检查临界尺寸（AEI CD），以及目标层的修剪时间。提供蚀刻装置，并且基于ADI CD，目标AEI CD和修剪时间确定蚀刻装置的内壁上的保护层的形成时间。形成预定形成时间的保护层，通过使用光致抗蚀剂图案作为掩模，对目标层进行修整时间的修整处理，以形成元件。

Public/Granted literature

US20150162206A1 METHOD FOR ETCHING TARGET LAYER OF SEMICONDUCTOR DEVICE IN ETCHING APPARATUS Public/Granted day:2015-06-11

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/02	.半导体器件或其部件的制造或处理
H01L21/04	..至少具有一个跃变势垒或表面势垒的器件，例如PN结、耗尽层、载体集结层
H01L21/18	...器件有由周期表Ⅳ族元素或含有/不含有杂质的AⅢBⅤ族化合物构成的半导体，如掺杂材料
H01L21/30	....用H01L21/20至H01L21/26各组不包含的方法或设备处理半导体材料的（在半导体材料上制作电极的入H01L21/28）
H01L21/302	.....改变半导体材料的表面物理特性或形状的，例如腐蚀、抛光、切割
H01L21/306	......化学或电处理，例如电解腐蚀（形成绝缘层的入H01L21/31；绝缘层的后处理入H01L21/3105）
H01L21/308	.......应用掩膜的（H01L21/3063，H01L21/3065优先）