发明授权
- 专利标题： Low-k interconnect structures with reduced RC delay
- 专利标题（中）： 具有降低RC延迟的低k互连结构
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申请号： US11585610申请日： 2006-10-24
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公开(公告)号： US09087877B2公开(公告)日： 2015-07-21
- 发明人: Chung-Chi Ko , Ting-Yu Shen , Keng-Chu Lin , Chia-Cheng Chou , Tien-I Bao , Shwang-Ming Jeng , Chen-Hua Yu
- 申请人： Chung-Chi Ko , Ting-Yu Shen , Keng-Chu Lin , Chia-Cheng Chou , Tien-I Bao , Shwang-Ming Jeng , Chen-Hua Yu
- 申请人地址： TW Hsin-Chu
- 专利权人： Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人： Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人地址： TW Hsin-Chu
- 代理机构： Slater & Matsil, L.L.P.
- 主分类号： H01L21/4763
- IPC分类号： H01L21/4763 ; H01L21/768
摘要：
A method for forming an integrated circuit includes forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, forming a dielectric barrier layer covering at least sidewalls of the opening, performing a treatment to improve a wetting ability of the dielectric barrier layer, and filling the opening with a conductive material, wherein the conductive material is in contact with the dielectric barrier layer.
公开/授权文献
- US20080096380A1 Low-k interconnect structures with reduced RC delay 公开/授权日：2008-04-24
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