发明授权
- 专利标题： Method for wafer level packaging and a package structure thereof
- 专利标题（中）： 晶圆级封装方法及其封装结构
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申请号： US14198493申请日： 2014-03-05
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公开(公告)号： US09087912B2公开(公告)日： 2015-07-21
- 发明人: Tsung Jen Liao
- 申请人： CHIPMOS TECHNOLOGIES INC
- 申请人地址： TW Hsinchu
- 专利权人： CHIPMOS TECHNOLOGIES INC.
- 当前专利权人： CHIPMOS TECHNOLOGIES INC.
- 当前专利权人地址： TW Hsinchu
- 代理商 Chun-Ming Shih
- 优先权： TW102131200A 20130830
- 主分类号： H01L23/48
- IPC分类号： H01L23/48 ; H01L23/00
摘要：
The present disclosure relates to a method for wafer level packaging and a package structure thereof. The method includes several steps. A through hole is formed in the interposer with a thickness that is less than the length of a first conducting pillar. The first conducting pillar is disposed inside the through hole. A redistribution layer is disposed and electrically connected with the first conducting pillar. A solder ball is disposed on the redistribution layer so as to form a wafer level packaging structure.