Invention Grant
- Patent Title: Semiconductor device having pinned layer with enhanced thermal endurance
- Patent Title (中): 具有增强耐热性的固定层的半导体器件
-
Application No.: US14254871Application Date: 2014-04-16
-
Publication No.: US09087977B2Publication Date: 2015-07-21
- Inventor: Jeong-Heon Park , Ki-Woong Kim , Hee-Ju Shin , Joon-Myoung Lee , Woo-Jin Kim , Jae-Hoon Kim , Se-Chung Oh , Yun-Jae Lee
- Applicant: Jeong-Heon Park , Ki-Woong Kim , Hee-Ju Shin , Joon-Myoung Lee , Woo-Jin Kim , Jae-Hoon Kim , Se-Chung Oh , Yun-Jae Lee
- Applicant Address: KR
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR
- Agency: Renaissance IP Law Group LLP
- Priority: KR10-2013-0096009 20130813
- Main IPC: H01L43/02
- IPC: H01L43/02 ; H01L43/08 ; H01F10/32 ; G11C11/16
Abstract:
A semiconductor device is provided having a free layer and a pinned layer spaced apart from each other. A tunnel barrier layer is formed between the free layer and the pinned layer. The pinned layer may include a lower pinned layer, and an upper pinned layer spaced apart from the lower pinned layer. A spacer may be formed between the lower pinned layer and the upper pinned layer. A non-magnetic junction layer may be disposed adjacent to the spacer or between layers in the upper or lower pinned layer.
Public/Granted literature
- US20150048464A1 SEMICONDUCTOR DEVICE HAVING PINNED LAYER WITH ENHANCED THERMAL ENDURANCE Public/Granted day:2015-02-19
Information query
IPC分类:
