An embodiments herein relate to a gate driving circuit and display device which include a plurality of shift registers. The gate driving circuit comprises: a plurality of shift registers, wherein each of the shift registers includes a plurality of stages which sequentially output a gate signal, wherein the stages of a kth shift register are activated when a kth SR selection signal generated as a first logic level voltage is input, and the stages of the kth shift register are not activated when the kth SR selection signal generated as a second logic level voltage is input, wherein k is a natural number equal to or less than the number of the shift registers.