Invention Grant
- Patent Title: 3D integrated heterostructures having low-temperature bonded interfaces with high bonding energy
- Patent Title (中): 具有低粘结界面的3D集成异质结构具有高的结合能
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Application No.: US14334370Application Date: 2014-07-17
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Publication No.: US09117686B2Publication Date: 2015-08-25
- Inventor: Gweltaz Gaudin
- Applicant: Soitec
- Applicant Address: FR Bernin
- Assignee: SOITEC
- Current Assignee: SOITEC
- Current Assignee Address: FR Bernin
- Agency: TraskBritt
- Priority: FR1056696 20100820
- Main IPC: H01L21/30
- IPC: H01L21/30 ; H01L29/06 ; H01L21/20 ; H01L21/762 ; H01L23/00 ; H01L25/065 ; H01L25/00 ; B81C3/00

Abstract:
The invention relates to a process for assembling a first element that includes at least one first wafer, substrate or at least one chip, and a second element of at least one second wafer or substrate, involving the formation of a surface layer, known as a bonding layer, on each substrate, at least one of the bonding layers being formed at a temperature less than or equal to 300° C.; conducting a first annealing, known as degassing annealing, of the bonding layers, before assembly, at least partly at a temperature at least equal to the subsequent bonding interface strengthening temperature but below 450° C.; forming an assembling of the substrates by bringing into contact the exposed surfaces of the bonding layers, and conducting an annealing of the assembled structure at a bonding interface strengthening temperature below 450° C.
Public/Granted literature
- US20140327113A1 3D INTEGRATED HETEROSTRUCTURES HAVING LOW-TEMPERATURE BONDED INTERFACES WITH HIGH BONDING ENERGY Public/Granted day:2014-11-06
Information query
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