发明授权
- 专利标题： Layout method to minimize context effects and die area
- 专利标题（中）： 布局方法，尽量减少上下文影响和模具面积
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申请号： US13622925申请日： 2012-09-19
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公开(公告)号： US09123562B2公开(公告)日： 2015-09-01
- 发明人: James Walter Blatchford , Thomas J. Aton
- 申请人： Texas Instruments Incorporated
- 申请人地址： US TX Dallas
- 专利权人： TEXAS INSTRUMENTS INCORPORATED
- 当前专利权人： TEXAS INSTRUMENTS INCORPORATED
- 当前专利权人地址： US TX Dallas
- 代理商 Jacqueline J. Garner; Frank D. Cimino
- 主分类号： H01L27/088
- IPC分类号： H01L27/088 ; H01L29/772 ; H01L21/8234 ; H01L27/02 ; H01L29/78
摘要：
An integrated circuit with an active geometry with a wide active region and with a narrow active region with at least one jog where said wide active region transitions to said narrow active region and where a gate overlies said jog. A method of making an integrated circuit with an active geometry with a wide active region and with a narrow active region with at least one jog where said wide active region transitions to said narrow active region, where a gate overlies said jog and where a gate overlies the wide active region forming a wide transistor.
公开/授权文献
- US20130069081A1 Layout Method To Minimize Context Effects and Die Area 公开/授权日：2013-03-21
信息查询
IPC分类:
