Invention Grant
- Patent Title: Encapsulation of closely spaced gate electrode structures
- Patent Title (中): 密封间隔栅电极结构的封装
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Application No.: US14086563Application Date: 2013-11-21
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Publication No.: US09123568B2Publication Date: 2015-09-01
- Inventor: Peter Baars , Richard Carter , Andy Wei
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Amerson Law Firm, PLLC
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L21/8234 ; H01L29/66 ; H01L29/78 ; H01L21/285 ; H01L23/485 ; H01L23/28

Abstract:
A semiconductor device includes a plurality of NMOS transistor elements, each including a first gate electrode structure above a first active region, at least two of the plurality of first gate electrode structures including a first encapsulating stack having a first dielectric cap layer and a first sidewall spacer stack. The semiconductor device also includes a plurality of PMOS transistor elements, each including a second gate electrode structure above a second active region, wherein at least two of the plurality of second gate electrode structures include a second encapsulating stack having a second dielectric cap layer and a second sidewall spacer stack. Additionally, the first and second sidewall spacer stacks each include at least three dielectric material layers, wherein each of the three dielectric material layers of the first and second sidewall spacer stacks include the same dielectric material.
Public/Granted literature
- US20140077308A1 ENCAPSULATION OF CLOSELY SPACED GATE ELECTRODE STRUCTURES Public/Granted day:2014-03-20
Information query
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