Invention Grant
- Patent Title: Method of manufacturing semiconductor wafers
- Patent Title (中): 制造半导体晶圆的方法
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Application No.: US14087883Application Date: 2013-11-22
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Publication No.: US09123795B2Publication Date: 2015-09-01
- Inventor: Yoshio Nakamura , Daizo Ichikawa , Haruo Sumizawa , Shiro Hara , Sommawan Khumpuang , Shinichi Ikeda
- Applicant: Fujikoshi Machinery Corp. , NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
- Applicant Address: JP Nagano JP Tokyo
- Assignee: FUJIKOSHI MACHINERY CORP.,NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
- Current Assignee: FUJIKOSHI MACHINERY CORP.,NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
- Current Assignee Address: JP Nagano JP Tokyo
- Agency: Birch, Stewart, Kolasch & Birch, LLP
- Priority: JP2012-265687 20121204
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/78

Abstract:
A method of manufacturing semiconductor wafers which facilitates formation of orientation flat lines and allows beveling work without problems. The method of manufacturing semiconductor wafers includes steps wherein a plurality of small-diameter wafers is cut out from a large-diameter semiconductor wafer, the method including: a marking step of forming straight groove-like orientation flat lines by a laser beam so as to cross the respective small-diameter wafers in each row in the large-diameter semiconductor wafer, wherein cutout positions of the small-diameter wafers are aligned in rows in a specific direction, collectively for each of the rows; and a cutting step of cutting out the small-diameter wafers separately from the large-diameter semiconductor wafer, by a laser beam, after the marking step, in such a way that the orientation flat lines are located at required positions in the small-diameter wafers to be obtained.
Public/Granted literature
- US20140154870A1 METHOD OF MANUFACTURING SEMICONDUCTOR WAFERS Public/Granted day:2014-06-05
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