发明授权
US09141549B2 Memory system with read and write caches and method of controlling memory system with read and write caches
有权
具有读和写高速缓存的内存系统和使用读写缓存控制内存系统的方法
- 专利标题： Memory system with read and write caches and method of controlling memory system with read and write caches
- 专利标题（中）： 具有读和写高速缓存的内存系统和使用读写缓存控制内存系统的方法
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申请号： US12542222申请日： 2009-08-17
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公开(公告)号： US09141549B2公开(公告)日： 2015-09-22
- 发明人: Hirokuni Yano , Naoki Otsuka
- 申请人： Hirokuni Yano , Naoki Otsuka
- 申请人地址： JP Tokyo
- 专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人地址： JP Tokyo
- 代理机构： Oblon, McClelland, Maier & Neustadt, L.L.P.
- 优先权： JP2008-335504 20081227
- 主分类号： G06F12/08
- IPC分类号： G06F12/08
摘要：
A controller sets, out of a data range that is specified in a read request from a host device, a predetermined size of a first data range that follows a top portion of the data range and a predetermined size of a second data range that follows the first data range, and after transfer, to the host device, of data corresponding to the first data range from a second storage unit or a third storage unit having smaller data output latency than the first storage unit in which read/write of data is performed is started, the controller searches for data corresponding to the second data range in the second storage unit or the third storage unit.
公开/授权文献
- US20100169549A1 MEMORY SYSTEM AND CONTROLLER 公开/授权日：2010-07-01
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